Magic Tecnica G3 User Manual

KSZ9692PBIntegrated Gigabit Networking andCommunications ControllerRev. 3.0Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408)

Micrel, Inc.KSZ9692PBAugust 200910M9999-082609-3.0NAND Flash Memory InterfaceThe KSZ9692PB NAND controller provides interface to external NAND Flash m

Micrel, Inc.KSZ9692PBAugust 200911M9999-082609-3.0Figure 7. 16-bit NAND Interface ExamplesDDR ControllerThe KSZ9692PB DDR memory controller provi

Micrel, Inc.KSZ9692PBAugust 200912M9999-082609-3.0A dedicated internal PLL provides clocking to the DDR memory controller and the two differential clo

Micrel, Inc.KSZ9692PBAugust 200913M9999-082609-3.0DDR memory controller access to memory bank is typically of the burst type. Figures 10 and 11 are ex

Micrel, Inc.KSZ9692PBAugust 200914M9999-082609-3.0SDIO/SD Host ControllerIntegrated SDIO/SD host controller provides interface for removable mass stor

Micrel, Inc.KSZ9692PBAugust 200915M9999-082609-3.0USB 2.0 InterfaceIntegrated dual USB 2.0 interface can be configured as 2-port host, or

Micrel, Inc.KSZ9692PBAugust 200916M9999-082609-3.0PCI InterfaceThe KSZ9692PB integrates a PCI-to-AHB bridge solution for interfacing with 32-bit PCI,

Micrel, Inc.KSZ9692PBAugust 200917M9999-082609-3.0A wake-up event is a request for hardware and/or software external to the network devi

Micrel, Inc.KSZ9692PBAugust 200918M9999-082609-3.0There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a

Micrel, Inc.KSZ9692PBAugust 200919M9999-082609-3.0See Signal Description list for detailed GPIO map.I2CThe I2C interface is a 2-pin (SCL & SDA) ge

Micrel, Inc.KSZ9692PBAugust 20092M9999-082609-3.0Block DiagramFigure 1. KSZ9692PB Block Diagram

Micrel, Inc.KSZ9692PBAugust 200920M9999-082609-3.0System Level InterfacesThe following figures illustrate the high-level system connections to

Micrel, Inc.KSZ9692PBAugust 200921M9999-082609-3.0Signal Descriptions by GroupPin NumberPin NamePin TypePin DescriptionSystem InterfaceR5RESETNIReset,

Micrel, Inc.KSZ9692PBAugust 200922M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionL3ECS2OExternal I/O Chip Select 2, asserted Low.Three Exter

Micrel, Inc.KSZ9692PBAugust 200923M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionDDR InterfaceT17, V18,U17, T16,W20, W19,Y20, Y19,W18, V17,U

Micrel, Inc.KSZ9692PBAugust 200924M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionP19P0_RXERIMII mode: RX errorRGMII mode: input SELM17P0_CRS

Micrel, Inc.KSZ9692PBAugust 200925M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionG16USBTESTO (Analog)USB analog test output (factory reserv

Micrel, Inc.KSZ9692PBAugust 200926M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionU20, U19TOUT[1:0]/GPIO[5:4]I/OTimer 1/0 out or General Purp

Micrel, Inc.KSZ9692PBAugust 200927M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionB1GNT1NOPCI Bus Grant 1Assert Low.In Host Bridge Mode, this

Micrel, Inc.KSZ9692PBAugust 200928M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionD9FRAMENI/OPCI Bus Frame signal, asserted Low.FRAMEN is an

Micrel, Inc.KSZ9692PBAugust 200929M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionE5PCLKOUT0OPCI Clock output 0.This signal provides the timi

Micrel, Inc.KSZ9692PBAugust 20093M9999-082609-3.0Applications∑ Enhanced residential gateways∑ High-end printer servers∑ Voice-over-Internet Protoco

Micrel, Inc.KSZ9692PBAugust 200930M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionTAP Control SignalsA18TCKIJTAG Test ClockA17TMSIJTAG Test M

Micrel, Inc.KSZ9692PBAugust 200931M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionL6PLLVDDA3.3PBand Gap Reference Analog Power. (1)M8PLLVSSA3

Micrel, Inc.KSZ9692PBAugust 200932M9999-082609-3.0Power-up Strapping OptionsCertain pins are sampled upon power up or reset to initialize K

Micrel, Inc.KSZ9692PBAugust 200933M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionM1EROEN(WRSTPLS)Ipd/OROM/SRAM/FLASH(NOR) and EXTIO Output E

Micrel, Inc.KSZ9692PBAugust 200934M9999-082609-3.0Pin NumberPin NamePin TypePin DescriptionT4NWENIpu/ONAND Write Enable, asserted lowDuring reset, thi

Micrel, Inc.KSZ9692PBAugust 200935M9999-082609-3.0Absolute Maximum Ratings(1)Supply Voltage(VDD1.2, PLLDVDD1.2, PLLSVDD1.2,USB1VDD1.2, USB2VDD1.2 ) ..

Micrel, Inc.KSZ9692PBAugust 200936M9999-082609-3.0Timing SpecificationsFigure 16 provides power sequencing requirement with respect to system reset.Fi

Micrel, Inc.KSZ9692PBAugust 200937M9999-082609-3.0Figure 18. Static Memory Write CycleSymbolParameter(1)RegistersRBiTACCProgrammable bank i access tim

Micrel, Inc.KSZ9692PBAugust 200938M9999-082609-3.0SymbolParameterMin(1)Typ(1)Max(1)UnitsTctaValid address to CS setup timeEBiTACS+0.8EBiTACS+1.1EBiTAC

Micrel, Inc.KSZ9692PBAugust 200939M9999-082609-3.0Signal Location Information1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20APMEN PAD28 PAD26 PAD21

Micrel, Inc.KSZ9692PBAugust 20094M9999-082609-3.0ContentsSystem Level Applications ...

Micrel, Inc.KSZ9692PBAugust 200940M9999-082609-3.0Package InformationFigure 21. 400-Pin PBGAMICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131

Micrel, Inc.KSZ9692PBAugust 20095M9999-082609-3.0List of FiguresFigure 3. KSZ9692PB Functional Block Diagram...

Micrel, Inc.KSZ9692PBAugust 20096M9999-082609-3.0System Level ApplicationsFigure 2. Peripheral Options and Examples

Micrel, Inc.KSZ9692PBAugust 20097M9999-082609-3.0Functional DescriptionThe KSZ9692PB is a highly integrated embedded application controller that is de

Micrel, Inc.KSZ9692PBAugust 20098M9999-082609-3.0ARM High-Performance ProcessorThe KSZ9692PB is built around the 16/32-bit ARM922T RISC proce

Micrel, Inc.KSZ9692PBAugust 20099M9999-082609-3.0Figure 4. Static Memory Interface ExamplesFigure 5. External I/O Interface Examples